FPGA Based Hardware Co-Simulation of an Area and Power Efficient FIR Filter for Wireless Communication Systems

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Authors

Rajesh KumarNational Institute of Technical Teachers Training and Research, Chandigarh
Swapna DeviNational Institute of Technical Teachers Training and Research, Chandigarh
S. S. PattnaikNational Institute of Technical Teachers Training and Research, Chandigarh

DOI Number
https://doi.org/ https://doi.org/10.15415/jtmge.2010.11008

Keywords
FPGA, PDA, Simulation Add/Shift, VHDL

Abstract

“In this paper FPGA based hardware co-simulation of an area and power efficient FIR filter for wireless communication systems is presented. The implementation is based on distributed arithmetic (DA) which substitutes multiply-and-accumulate operations with look up table (LUT) accesses. Parallel Distributed arithmetic (PDA) look up table approach is used to implement an FIR Filter taking optimal advantage of the look up table structure of FPGA using VHDL. The proposed design is hardware co-simulated using System Generator10.1, synthesized with Xilinx ISE 10.1 software, and implemented on Virtex-4 based xc4vlx25-10ff668 target device. Results show that the proposed design operates at 17.5 MHz throughput and consumes 0.468W power with considerable reduction in required resources to implement the design as compared to Coregen and add/shift based design styles. Due to this reduction in required resources the proposed design can also be implemented on Spartan-3 FPGA device to provide cost effective solution for DSP and wireless communication applications.”

References

Allred, D.J. Yoo, H., Krishnan, V. Huang, W. and Anderson, D. (2004) ‘A Novel High Performance Distributed Arithmetic Adaptive Filter Implementation on an FPGA’, Proceedings IEEE International. Conference on Acoustics, Speech, and Signal Processing (ICASSP’04), 5,161-164.

Banerjee, P., Haldar, M., Zaretsky, D. and Robert Anderson (2004) ‘Overview of a compiler for synthesizing Matlab programs onto FPGAs’, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12: 3, 312-324.

Longa, P. and Miri, A. (2006) ‘Area-Efficient FIR Filter Design on FPGAs using Distributed Arithmetic’, IEEE International Symposium on Signal Processings and Information Technology, p. 248-252.

Macpherson, K.N. and Stewart, R.W. (2006) ‘Area efficient FIR filters for high speed FPGA Implementation’, IEE Proceedings-Visual Image Signal Process, 153: 6, 711-720.

Mirzaei, S., Hosangadi, A. and Kastner, R. (2006) ‘FPGA Implementation of High Speed FIR Filters Using Add and Shift Method’, paper presented at the IEEE International Conference on Computer Design, ICCD.

Ownby, M. and Mahmoud, W.H. (2002) ‘A Design methodology for implementing DSP with Xilinx System Generator for Matlab’, IEEE, p. 404-408.

White, S. A. (1989) ‘Applications of distributed arithmetic to digital signal processing: A tutorial review’, IEEE ASSP Magazine, 6, 4–19.

Yoo, H. and Anderson, D.V. (2005) ‘Hardware-Efficient Distributed Arithmetic Architecture for High-Order Digital Filters’, Proceedings IEEE, ICASSP, pp. V125-128.

Zack, S. and Dhanani, S. (2004) ‘DSP Co-Processing in FPGAs Embedding High Performance, Low-Cost DSP Functions’, WP212 (v1.0).

How to Cite

Rajesh Kumar, Swapna Devi, S. S. Pattnaik. FPGA Based Hardware Co-Simulation of an Area and Power Efficient FIR Filter for Wireless Communication Systems. J.Technol. Manag. Grow. Econ.. 2023, 01, 113-122

FPGA Based Hardware Co-Simulation of an Area and Power Efficient FIR Filter for Wireless Communication Systems

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